IRAUDAMP4【PDF 4/21 页】KIT 2CH 120W HALF BRDG AUDIO AMP

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Sheet目录1221

1页 2页 3页 [4页]5页 6页 7页 8页

IRS20955(S)PbF

Electrical Characteristics

V CC ,V BS = 12 V, I DD =5 mA, V SS =20 V, V S =0 V,C L =1 nF and T A =25 ° C unless otherwise specified.

Symbol

Definition

Min

Typ

Max

Units

Test Conditions

Low-Side Supply

UV CC+

UV CC-

V CC supply UVLO positive threshold

V CC supply UVLO negative threshold

8.4

8.2

8.9

8.7

9.4

9.2

V

I QCC

V CLAMPL

Low-side quiescent current

Low-side Zener diode clamp voltage

-

19.6

-

20.4

3

21.6

mA

V

V DT = V CC

I CC =5 mA

High-Side Floating Supply

UV BS+

UV BS-

I QBS

High-side well UVLO positive

threshold

High-side well UVLO negative

threshold

High-side quiescent current

8.0

7.8

-

8.5

8.3

-

9.0

8.8

1

V

mA

I LKH

V CLAMPH

High-side to low-side leakage current

High-side Zener diode clamp voltage

-

19.6

-

20.4

50

21.6

μA

V

V B =V S =200 V

I BS =5 mA

Floating Input Supply

UV DD+

V DD , V SS floating supply UVLO

positive threshold

8.2

8.7

9.2

V SS =0 V

UV DD-

I QDD

V CLAMPM

I LKM

V DD , V SS floating supply UVLO

negative threshold

Floating input quiescent current

Floating input Zener diode clamp

voltage

Floating input side to low-side leakage

current

7.7

-

9.8

-

8.2

-

10.2

-

8.7

1

10.8

50

V

mA

V

μA

V SS =0 V

V DD =9.5 V +V SS

I DD =5 mA

V DD =V SS =200 V

Floating PWM Input

V IH

V IL

Logic high input threshold voltage

Logic low input threshold voltage

2.3

-

1.9

1.9

-

1.5

V

I IN+

I IN-

Logic “1” input bias current

Logic “0” input bias current

-

-

-

-

40

1

μA

V IN =3.3 V

V IN = V SS

Protection

V REF

V th,OCL

Reference output voltage

Low-side OC threshold in V S

4.8

1.1

5.1

1.2

5.4

1.3

I OREF =0.5 mA

OCSET=1.2 V, Fig. 3

V th,OCH

V th,1

V th,2

I CSD+

I CSD-

t SD

t OCH

t OCL

High-side OC threshold in V CSH

CSD pin shutdown release threshold

CSD pin self reset threshold

CSD pin discharge current

CSD pin charge current

Shutdown propagation delay from

V CSD > V SS + V th,OCH to shutdown

Propagation delay time from V CSH >

V th,OCH to shutdown

Propagation delay time from V S >

V th,OCL to shutdown

1.1+ V S

0.62 x V DD

0.26 x V DD

70

70

-

-

-

1.2+ V S

0.70 x V DD

0.30 x V DD

100

100

-

-

-

1.3+ V S

0.78 x V DD

0.34 x V DD

130

130

250

500

500

V

μA

ns

V S =200 V, Fig. 4

V SS =0 V

V SD = V SS +5 V

Fig. 2

Fig. 4

Fig. 3

Gate Driver

I o+

Output high short circuit current

(source)

-

1.0

-

A

V O =0 V, PW<10 μs

I o-

V OL

Output low short circuit current (sink)

Low level output voltage

LO – COM, HO – VS

-

-

1.2

-

-

0.1

V

V O =12 V, PW<10 μs

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